The present invention relates to a multi-speed logic analyzer which can measure one block of input logic data with a high frequency clock while measuring the same or another block of input logic data with a low frequency clock.
Logic measurement instruments are necessary to meet the need for calibrating or troubleshooting sophisticated digital electronic apparatus, particularly those that are microprocessor based. One such logic measurement instrument is a logic analyzer which stores input logic data in a memory and displays the stored data on a display device such as a cathode-ray tube. The logic analyzer is a very useful and versatile tool, because among other things, it can detect the desired word from the input data and measure the desired portions of the input data by reference to the desired word.
It is sometimes desirable to measure certain portions of one block of input data, such as control data, in detail using a high frequency clock while measuring the same or another block of input data, such as an address data, at a slower clock rate, because the operator can observe both the entire block of data as well as the portion of interest. However, conventional logic analyzers acquire the input data with the same clock frequency, and cannot acquire the input data (simultaneously) with different clock frequencies. Moreover, conventional logic analyzers cannot detect different trigger words for each block of input data, so that the operator cannot simultaneously observe different portions of the input data. Even if two or more logic analyzers are employed at the same time for measuring the input data with different clock frequencies and different trigger words for each logic analyzer, it is difficult to know the time relationships of the different clocks and different trigger words.